In integrated circuit design, circuits for commonly used functions, such as AND gates, OR gates, etc., are often combined into "cells," and a model is created for each cell. These models are used in circuit simulation to provide a simpler model of the cell than would be provided by simulating each of the components within a cell. Typically, the model is used to determine the delay of a signal through the cell, the transition time of the output signal, the input capacitance and power dissipation values for the cell.
IBM Corporation (IBM is a registered trademark of International Business Machines Corporation) has used an early timing estimator (ETE) equation for modeling the delay of a signal through a cell. This equation was optimized for multistate circuit designs over a limited operating range of input transition and output capacitive loads. For a detailed description of ETE see EDS manual 3325 "Early Timing Estimator (ETE) User's Guide and Reference." This equation has been outdated by advances in submicron silicon technologies and faster cycle times (greater than 150 megahertz). With the increased speed of submicron integrated circuits, the current ETE equation has led to unacceptable errors, e.g., errors that are often as large as the total delay between gates. What is needed is a method for generating an improved model for evaluating the operation of an integrated circuit design. It is an object of the present invention to improve the accuracy of the ETE equation by generating a high performance delay/transition equation which reduces the average propagation delay error and provides more consistent accuracy over a wider operating range.